The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas, For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complimentary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacture of such devices is the formation of isolation areas to electrically separate electrical components, or portion thereof, that are closely integrated in the silicon wafer. Isolation areas are often implemented using a shallow trench isolation (STI) process to form shallow trenches and fill it with oxide. Deep trenches, or variations of the deeptype and shallow-type trenches, are used as well. Trench isolation is often used to separate diffusion regions in a MOS-based device. While the particular structure of a given active device can vary between device types, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. A trench isolation region is often used to separate one active area from the others.
Trenches are typically formed in the silicon through the use of well-known photolithography and etching techniques. In advanced, deep-submicron manufacturing processes, an important objective of the etching process is to terminate the etching at a precise depth, and this is readily achieved using a conventional endpoint detection system. When etching one film on top of a different film, the amount of light for one particular wavelength emitted by the plasma changes as the top film is being etched away. This wavelength of light corresponds to one of the products during the plasma etch process. The endpoint detection system is used to detect the changes of that one particular length of the light during the plasma etching process. There are two conditions that apply to such an endpoint detection system: the film on the top to be etched has finite thickness relative to the etchrate of the film; and there is another film of a different type underneath the film to be etched. Therefore, as the top film is being etched away, the products change and this, in turn, changes the amount of the light emitted by those products. As a result, the endpoint detection system can pick up the changes in the intensity of the light and terminate the etching process when the top film is completely etched away.
Etching an isolation trench is more difficult. When etching an isolation trench, the film to be etched is typically the silicon substrate which is several millimeters thick. Also, there is not another film underneath. So for the trench etch (shallow or deep), there is no endpoint detection system available to terminate the etching process. The common method to stop the etch process at a precise depth is to tightly control the etchrate. But etchrates usually fluctuate from day to day, and also after a major clean, such as a wet clean. To control the depth of the trench, the operator must often perform an etchrate check before processing a lot, and then adjust the etch time accordingly when the etchrate changes.
Accordingly, there has been a long-standing need for semiconductor structures, and manufacturing processes therefore, that overcome the aforementioned disadvantages of the prior art.